1. Field of the Invention
The present invention relates generally to data communications, and more particularly to performance testing of high speed data links.
2. Description of the Related Art
A data communications network is the interconnection of two or more communicating entities (i.e., data sources and/or sinks) over one or more data links. A data communications network allows communication between multiple communicating entities over one or more data communications links. High bandwidth applications supported by these networks include streaming video, streaming audio, and large aggregations of voice traffic. In the future, the demands for high bandwidth communications are certain to increase. To meet such demands, an increasingly popular alternative is the use of lightwave communications carried over fiber optic cables. The use of lightwave communications provides several benefits, including high bandwidth, ease of installation, and capacity for future growth.
The synchronous optical network (SONET) protocol is among several protocols designed to employ an optical infrastructure. SONET is widely employed in voice and data communications networks. SONET is a physical transmission vehicle capable of transmission speeds in the multi-gigabit range, and is defined by a set of electrical as well as optical standards. A similar standard to SONET is the Synchronous Digital Hierarchy (SDH) which is the optical fiber standard predominantly used in Europe. There are only minor differences between the two standards. Accordingly, hereinafter any reference to the term SONET refers to both SDH and SONET networks, unless otherwise noted.
SONET utilizes a byte-interleaved multiplexing scheme. Multiplexing enables one physical medium to carry multiple signals. Byte interleaving simplifies multiplexing and offers end-to-end network management. Each STS is transmitted on a link at regular time intervals (for example, 125 microseconds) and grouped into frames. See Bellcore Generic Requirements document GR-253-CORE (Issue 2, December 1995), hereinafter referred to as xe2x80x9cSONET Specification,xe2x80x9d and incorporated herein by reference for all purposes. The first step in the SONET multiplexing process involves the generation of the lowest level or base signal. In SONET, this base signal is referred to as synchronous transport signalxe2x80x94level 1, or simply STS-1, which operates at 51.84 Mbps (Megabits per second). Data between adjacent nodes is transmitted in these STS modules. Higher-level signals are integer multiples of STS-1, creating the family of STS-N signals in Table 1. An STS-N signal is composed of N byte-interleaved STS-1 signals. Table 1 also includes the optical counterpart for each STS-N signal, designated optical carrier level N (OC-N).
SONET organizes STS datastreams into frames, consisting of transport overhead and a synchronous payload envelope. The overhead consists of information that allows the network to operate and allow communications between a network controller and nodes. The transport overhead includes framing information and pointers, and performance monitoring, communications, and maintenance information. The synchronous payload envelope is the data to be transported throughout the network, from node to node until the data reaches its destination.
In a data communication network transporting OC-192 signals at 9.953280 Gbps (Giga bits per second), it is impractical to clock all devices at that high rate. In digital transmission, a clock refers to a series of repetitive pulses that keep the bit rate of data constant and indicate the location of ones and zeroes in a data stream. Instead of clocking all devices at the high data stream rate, data is often transferred between devices at lower data rates, then increased to the higher data rate. For example, a serial bit stream operating at a high data rate can be de-serialized into 16 parallel bits and clocked at {fraction (1/16)}th the high data rate and later serialized again running at the higher data rate without changing the amount of data throughput. A framing logic device manipulates the data stream at clock rates ranging from 38.88 MHz to 622.08 MHz. The framing logic device (also referred to as a xe2x80x9cframerxe2x80x9d) transmits a 16-bit parallel data stream to a serializer at 622.08 MHz. The serializer sends the parallel data stream as a bit wide data stream at 9.953280 GHz.
The system components must be highly reliable and have good mark ratio tolerance transferring data at these high rates. Mark ratio tolerance is the amount of data density variance a signal path can tolerate before taking bit errors. A signal path requires a minimum signal toggle rate between 1""s and 0""s to keep the system functioning and DC balanced. Data density is the DC average of the signal. FIGS. 1A-1C illustrate a bit stream having varying mark ratios and data densities. FIG. 1A illustrates a bit stream with a mark ratio of 4/8 represented by four 1""s for every four 0""s. FIG. 1A has a 50% data density represented by the dotted line. FIG. 1B illustrates a bit stream with a mark ratio of 2/8 represented by two 1""s for every six 0""s. FIG. 1B has a 25% data density represented by the dotted line. FIG. 1C illustrates a bit stream with a mark ratio of 6/8 represented by six 1""s for every two 0""s. FIG. 1C has a 75% data density represented by the dotted line. A data communication network node goes though rigorous mark ratio tolerance testing prior to product release. A circuit that can transmit data with a mark ratio of 1/8 is considered to be a robust design.
The high speed signal path including signal lines, cables, and components such as optical transmitters and optical receivers are tested for mark ratio tolerance during design verification, circuit board test and system test before product release. Normally, a designer is dependent on random data from an LFSR (linear feedback shift register) to check for data dependencies in an optical transmitter or receiver. A pseudo-random bit stream (PRBS) is used to test components in a signal path for sensitivity to high ones or zeros density. A PRBS allows every combination of 1""s and 0""s to be tested. System performance information can be derived by analyzing the signal path""s eye pattern from the PRBS on an oscilloscope display. An open eye pattern corresponds to minimal signal distortion. A closed eye pattern corresponds to distortion of the signal waveform due to various errors such as pattern dependency and noise. To improve a circuit""s mark ratio tolerance, different circuit improvements can be implemented such as changing the line termination, changing the sensitivity of various components, and increasing or decreasing capacitor size. Various components of a data communications node must meet certain minimum mark ratio tolerance standards prior to product release and must go through rigorous qualification testing.
Determining the mark ratio tolerance of an entire system using a PRBS is difficult since a signal path typically consists of multiple components, cabling, and often performs serializing and de-serializing of the data. A PRBS that creates a data density of 50% on a serial line may create a data density of 100% or 0% on parallel signal lines creating differing mark ratios for different portions of the same signal path. For example, considering a parallel four-bit signal path that is later serialized into a one bit signal path, a PRBS of xe2x80x9c1010xe2x80x9d creates a data density of 50% on the one bit signal path, a data density of 100% on the first and third bits of the parallel signal path, and a data density of 0% on the second and fourth bits of the parallel signal path. The signal path often has capacitors connected serially on the signal path to AC couple devices, such as integrated circuits, of different technologies to level shift between different voltage ranges. Parallel AC coupled signal paths do not perform well under certain test conditions and give erroneous mark ratio tolerance failures. AC coupling of a parallel path often precludes the use of repetitive test patterns. DC drift on the capacitors during the mark ratio testing results in bit errors often causing the signal path to effectively shut down and stop functioning. Previous solutions required the signal path to be tested in pieces, giving only partial results or unreliable overall system mark ratio tolerance results. Other solutions include using extremely large capacitors such that the effects of DC drift takes longer to accumulate. This solution is undesirable due to the need to perform measurements in a short amount of time before the capacitors fully charge. In addition, these large capacitors use a large amount of board space and can be costly.
A method and apparatus of testing a signal path for mark ratio tolerance is needed that can be automatic, provide for varying data densities, and test all parallel signal lines and serial signal lines including AC coupled lines. The test circuitry must allow for testing at high data rates while still allowing for traditional test equipment to be utilized.
Accordingly, a method and apparatus for testing a signal path for mark ratio tolerance is provided that is automatic, provides for varying data densities, and tests all parallel signal lines and serial signal lines including AC coupled lines. The test circuitry allows for testing at high data rates while still allowing for traditional test equipment to be utilized. The method includes generating a varying test pattern by selecting between a first pattern and a second pattern according to a defined sequence; and sending the varying test pattern over the signal path. The mark ratio tolerance of a system can be tested, varying the data density of one portion of the signal path while maintaining a constant data density on another portion of the signal path.
According to an embodiment, generating the varying test pattern includes writing a value to a pattern register, writing a value to mode register, and enabling test circuitry to vary the value written to the pattern register according to the value written to the mode register.
Another embodiment of the invention is directed to an apparatus which includes a selection circuit for generating a varying test pattern to send over the signal path, the selection circuit generating the varying test pattern by selecting between a first pattern and a second pattern according to a select sequence signal, and a sequencer coupled to the selection circuit, the sequencer providing the select sequence signal to the selection circuit, the sequencer generating the select sequence signal according to a mode value.
In one embodiment, the second pattern is an inversion of the first pattern. In another embodiment, the data density is varied to determine the mark ratio tolerance limits of the signal path.
In one embodiment the apparatus is implemented as an application specific integrated circuit (ASIC) and disposed on a line card in a synchronous optical network (SONET).
Another embodiment of the invention is directed to a computer program product for communication. The computer program product includes signal bearing media bearing programming adapted to generate a varying test pattern by selecting between a first pattern and a second pattern according to a defined sequence; and sending the varying test pattern over the signal path.
Another embodiment is directed to a communication system including means for generating a varying test pattern by selecting between a first pattern and a second pattern according to a defined sequence, and means for sending the varying test pattern over a signal path. The signal path has a first portion and a second portion, wherein the first portion is a one bit serial path and the second portion is a N bit parallel path. The mark ratio tolerance of a system can be tested, varying the data density of one portion of the signal path while maintaining a constant data density on another portion of the signal path.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. As will also be apparent to one of skill in the art, the operations disclosed herein may be implemented in a number of ways, and such changes and modifications may be made without departing from this invention and its broader aspects. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.